### Cvičení 2

neručím za správnost, pokud mě doplní, kdo si je jistější budu rád:

#### 1.

```module KonecnyAutomat(input x, clk, reset,
output [2:0] y);

reg [2:0] state, nextstate;

parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;

always @ (posedge clk, posedge reset)
if (reset) state = S0;
else state = nextstate;

always @(*)
case (state)
S0: if (x) nextstate = S4;
else nextstate = S1;
S1: if (x) nextstate = S0;
else nextstate = S2;
S2: if (x) nextstate = S1;
else nextstate = S3;
S3: if (x) nextstate = S2;
else nextstate = S4;
S4: if (x) nextstate = S3;
else nextstate = S0;
default: nextstate = S0;
endcase

assign y = state;

endmodule```

#### 4.

```module mux2x1(in0, in1, select, out);
input [31:0] in0;
input [31:0] in1;
input select;
output [31:0] out;
assign out = select ? in1 : in0;
endmodule```
```module mux3x1(in0, in1, in2, select, out);
input [31:0] in0;
input [31:0] in1;
input [31:0] in2;
input [1:0] select;
output [31:0] out;
case (select)
2'b00: assign out = in0;
2'b01: assign out = in1;
2'b10: assign out = in2;
default: assign out = in0;
endcase
endmodule```
```module sumator(a, b, suma);
input [31:0] a;
input [31:0] b;
output [31:0] suma;
assign suma = a+b;
endmodule```
```module mul4(in, out);
input [31:0] in;
output [31:0] out;
assign out = 4*in;
endmodule```
```module compare(a, b, out);
input [31:0] a;
input [31:0] b;
output out;
assign out = (a == b) ? 1 : 0;
endmodule```
```module extend(
input [15:0] in,
output [31:0] out
);
assign out = { {16{in[15]}}, in };
endmodule```
```module registr(
input [31:0] in,
input enable,
input reset,
input clk,
output [31:0] out
);
reg [31:0] data = 0;
always @ (posedge clk, posedge reset)
if (reset) data = 0;
else if (enable) data = in;
assign out = data;
endmodule```
```module pole(
input [31:0] in,
input enable,
input clk,
output [31:0] out0,
output [31:0] out1
);
reg[31:0] regs[0:31];
reg [5:0] i;
initial begin
for (i=0;i<=31;i=i+1) regs[i] = 0; //initialize registers--just so they aren?t cares
end
always @ (posedge clk)
endmodule```
```module alu(
input [31:0] srcA,
input [31:0] srcB,
input [2:0] ALUcontrol,
output [31:0] ALUout,
output zero
);
reg[31:0] out=0;
always @(*)
case (ALUcontrol)
3'b010: out = srcA + srcB;
3'b110: out = srcA - srcB;
3'b000: out = srcA & srcB;
3'b001: out = srcA | srcB;
3'b011: out = srcA ^ srcB;
3'b111: out = (srcA < srcB) ? 1 : 0;
default: out = 0;
endcase
assign ALUout = out;
assign zero = (out==0) ? 1 : 0;
endmodule```
courses/a4m36pap/cviceni2.txt · Poslední úprava: 2019/01/10 18:46 (upraveno mimo DokuWiki)
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