Cvičení 4

1.

```module sum(c, pg, p, s);
input c;
input pg;
input p;
output s;
assign s = c ? pg : p;
endmodule```
```module pg(x, y, g, p, pg);
input x;
input y;
output g;
output p;
output pg;
assign g = x & y;
assign pg = y ? x : ~x;
assign p = ~pg;
endmodule```

2.

```module cla(p0, g0, p1, g1, p2, g2, p3, g3, c0, c1, c2, c3, Gg, Gp);
input p0;
input g0;
input p1;
input g1;
input p2;
input g2;
input p3;
input g3;
input c0;
output c1;
output c2;
output c3;
output Gg;
output Gp;
assign c1 = g0 | p0 & c0;
assign c2 = g1 | p1 & g0 | p1 & p0 & c0;
assign c3 = g2 | p2 & g1 | p2 & p1 & g0 | p2 & p1 & p0 & c0;
assign Gg = g3 | p3 & g2 | p3 & p2 & g1 | p3 & p2 & p1 & g0;
assign Gp = p3 & p2 & p1 & p0;
endmodule```

3.

```module clasum4(x, y, cin, s, p, g, cout);
input [3:0] x;
input [3:0] y;
input cin;
output [3:0] s;
output [3:0] p;
output [3:0] g;
output cout;
wire c1, c2, c3;

assign g[0] = x[0] & y[0], g[1] = x[1] & y[1], g[2] = x[2] & y[2], g[3] = x[3] & y[3];
assign p[0] = x[0] ^ y[0], p[1] = x[1] ^ y[1], p[2] = x[2] ^ y[2], p[3] = x[3] ^ y[3];

assign c1 = g[0] | (p[0] & cin);
assign c2 = g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);
assign c3 = g[2] | (p[2] & g[1]) | (p[2] & p[1]) | (p[2] & p[1] & p[0] & cin);
assign cout = g[3] | (p[3] & g[2]) | (p[3] & p[2]) | (p[3] & p[2] & p[1]) | (p[3] & p[2] & p[1] & p[0] & cin);

assign s[0] = cin ^ p[0], s[1] = c1 ^ p[1], s[2] = c2 ^ p[2], s[3] = c3 ^ p[3];
endmodule```

Alternativní řešení 4bit sčítačky pomocí modulů viz výše:

```module add4(x, y, c, s, Gp, Gg);
input [3:0] x;
input [3:0] y;
input c;
output [3:0] s;
output Gp;
output Gg;
wire p0, g0, pg0, p1, g1, pg1, p2, g2, pg2, p3, g3, pg3, c1, c2, c3;
sum sum0(c, pg0, p0, s[0]);
sum sum1(c1, pg1, p1, s[1]);
sum sum2(c2, pg2, p2, s[2]);
sum sum3(c3, pg3, p3, s[3]);
pg pg_0(x[0], y[0], g0, p0, pg0);
pg pg_1(x[1], y[1], g1, p1, pg1);
pg pg_2(x[2], y[2], g2, p2, pg2);
pg pg_3(x[3], y[3], g3, p3, pg3);
cla cla(p0, g0, p1, g1, p2, g2, p3, g3, c, c1, c2, c3, Gg, Gp);
endmodule```
```module add16(x, y, c, s, Sp, Sg);
input [15:0] x;
input [15:0] y;
input c;
output [15:0] s;
output Sp;
output Sg;
wire Gp0, Gg0, Gp1, Gg1, Gp2, Gg2, Gp3, Gg3, c, Gc1, Gc2, Gc3;
cla gcla(Gp0, Gg0, Gp1, Gg1, Gp2, Gg2, Gp3, Gg3, c, Gc1, Gc2, Gc3, Sg, Sp);
endmodule```
```module add64(x, y, c, s, Np, Ng, cout);
input [63:0] x;
input [63:0] y;
input c;
output [63:0] s;
output Np;
output Ng;
output cout;
wire Sp0, Sg0, Sp1, Sg1, Sp2, Sg2, Sp3, Sg3, c, Sc1, Sc2, Sc3;